CPE 312-COMPUTER ORGANIZATION

 

2002-03 Catalog Data: Organization of computer systems: Central processing unit; microprogrammed control; input/output organization; interrupts; traps; direct memory access; arithmetic operations; main memory;

3 lectures hours, 3 semester hours.

Prerequisite CPE 315

 

Textbook:

            Computer Architecture: A quantitative approach – third edition

            By David A. Patterson and John L. Hennessey, Morgan Kaufmann 2003.

 

Reference Books:

            Computer Architecture: A quantitative approach – second edition

            By David A. Patterson and John L. Hennessey, Morgan Kaufmann 1996.

 

Computer Organization and Architecture, by Linda Null and Julia Labour, Jones and Bartlett Publishers, 2003.

 

Coordinator:   Ausif Mahmood, Professor, Computer Science and Engineering

Phone: 203-576-4737, Email: mahmood@bridgeport.edu

 

Goals: The course is intended to teach computer architecture and design by first presenting the design of a small 8-bit processor and then the complete design of a fully pipelined 32 bit RISC processor.

 

Prerequisites by Topic:

  1. Boolean Algebra
  2. Design of combinational and sequential circuits.
  3. System level Digital Design
  4. A programming language such as “C” or “C++”.
  5. Describing and simulating digital designs in VHDL

 

TOPICS:

1.      Review of Digital System Design( Datapath + Control)             (5 hrs)

High speed addition, latches vs. edge triggered flip flops,

delay and clocking issues,

Register transfer issues, Controller architecture

(One hot vs. Log2n, )

                 ALU Design including multiplier, divide and square root units.

2.  Design of a small 8-bit Processor                                              (4 hrs)

Instruction set and assembly language design

Datapath, ALU design

Control sequence design

3.   Micro programmed control                                                      (4 hrs)

Micro-programmable controller architectures

Micro-assembly language

Implementing a computer’s controller using micro-programmed

controller.

4.   Design of a 32 bit RISC pipelined processor                            (4 hrs)

Fundamental ideas in a RISC architecture

Instruction set and assembly language design

Datapath, ALU design for the 32 bit processor

Control sequence design.

5.   Mid term Test                                       .                                (1.5 hrs)

6.   Design of pipelining for the RISC processor                             (10 hrs)

Hazards in pipelining, their detection and stalls.

Structural, data and control hazards, forwarding and branch

Prediction schemes to reduce pipelining stalls.

Compiler Optimization techniques to reduce hazards.

7.   Virtual, cache, associative memory design                                             (4 hrs)

8.   DMA and Interrupt design                                                                    (3 hrs)

9.  Floating point instruction and pipelining                                      (if time permits)

             issues

10.   Final Exam                                                                                         (2 hrs)

 

Computer Usage:

VHDL simulation on UNIX workstation or PCs.

 

Laboratory Projects: None.

 

Class Schedule: 3 class hours per week.

 

Contribution of course to meeting the professional component:

            This course contributes to the hardware design component as the students design different parts of a processor (ALU design, pipelined CPU design, interrupt, cache/virtual memory design) in different assignments in the course.

 

Estimated ABET Category:    Engineering Science – 1.5 credit hour or 50%

                                                Engineering Design -   1.5 credit or 50%

Grading:              one midterm    : 35%

                           Final Exam      : 45%

                           Assignments    : 20%

 

Prepared by: Ausif Mahmood, January 2003.